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# Created by write_sdc on Tue Nov 14 12:09:26 2023

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set sdc_version 2.1

set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA
set_max_area 0
set_load -pin_load 0.2 [get_ports {bcd_out_reg[11]}]
set_load -pin_load 0.2 [get_ports {bcd_out_reg[10]}]
set_load -pin_load 0.2 [get_ports {bcd_out_reg[9]}]
set_load -pin_load 0.2 [get_ports {bcd_out_reg[8]}]
set_load -pin_load 0.2 [get_ports {bcd_out_reg[7]}]
set_load -pin_load 0.2 [get_ports {bcd_out_reg[6]}]
set_load -pin_load 0.2 [get_ports {bcd_out_reg[5]}]
set_load -pin_load 0.2 [get_ports {bcd_out_reg[4]}]
set_load -pin_load 0.2 [get_ports {bcd_out_reg[3]}]
set_load -pin_load 0.2 [get_ports {bcd_out_reg[2]}]
set_load -pin_load 0.2 [get_ports {bcd_out_reg[1]}]
set_load -pin_load 0.2 [get_ports {bcd_out_reg[0]}]
set_ideal_network -no_propagate  [get_ports rst]
create_clock [get_ports clk]  -period 2.5  -waveform {0 1.25}
set_clock_latency -max 0.25  [get_clocks clk]
set_clock_latency -source 0.25  [get_clocks clk]
set_clock_uncertainty 0.125  [get_clocks clk]
set_clock_transition -max -rise 0.025 [get_clocks clk]
set_clock_transition -max -fall 0.025 [get_clocks clk]
set_clock_transition -min -rise 0.025 [get_clocks clk]
set_clock_transition -min -fall 0.025 [get_clocks clk]
set_false_path   -from [get_ports rst]
set_input_delay -clock clk  -max 1  [get_ports rst]
set_input_delay -clock clk  -min 0  [get_ports rst]
set_input_delay -clock clk  -max 1  [get_ports {bcd_in[7]}]
set_input_delay -clock clk  -min 0  [get_ports {bcd_in[7]}]
set_input_delay -clock clk  -max 1  [get_ports {bcd_in[6]}]
set_input_delay -clock clk  -min 0  [get_ports {bcd_in[6]}]
set_input_delay -clock clk  -max 1  [get_ports {bcd_in[5]}]
set_input_delay -clock clk  -min 0  [get_ports {bcd_in[5]}]
set_input_delay -clock clk  -max 1  [get_ports {bcd_in[4]}]
set_input_delay -clock clk  -min 0  [get_ports {bcd_in[4]}]
set_input_delay -clock clk  -max 1  [get_ports {bcd_in[3]}]
set_input_delay -clock clk  -min 0  [get_ports {bcd_in[3]}]
set_input_delay -clock clk  -max 1  [get_ports {bcd_in[2]}]
set_input_delay -clock clk  -min 0  [get_ports {bcd_in[2]}]
set_input_delay -clock clk  -max 1  [get_ports {bcd_in[1]}]
set_input_delay -clock clk  -min 0  [get_ports {bcd_in[1]}]
set_input_delay -clock clk  -max 1  [get_ports {bcd_in[0]}]
set_input_delay -clock clk  -min 0  [get_ports {bcd_in[0]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[11]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[11]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[10]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[10]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[9]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[9]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[8]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[8]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[7]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[7]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[6]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[6]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[5]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[5]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[4]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[4]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[3]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[3]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[2]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[2]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[1]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[1]}]
set_output_delay -clock clk  -max 1  [get_ports {bcd_out_reg[0]}]
set_output_delay -clock clk  -min 0  [get_ports {bcd_out_reg[0]}]
